Write Verilog code in the style shown in Figure 5.51 that represents a ring counter. Your code should have a parameter n that sets the number of flip-flops in the counter.

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module shiftn (R, L, w, Clock, Q); parameter n = 16; input [n-1:0] R; input L, w, Clock; output reg [n-1:0] Q; integer k; always @(posedge Clock) if (L) Q<=R; else begin for (k = 0; k< n-1; k=k+1) Q[k] <= Q[k+1]; Q[n-1] <= w; end endmodule