2. Assume a full-bypass circuit. Draw the pipeline chart showing all the bypass flow and register...

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2. Assume a full-bypass circuit. Draw the pipeline chart showing all the bypass flow and register access flow on the diagram, for the following MIPS code sequence. Assume there are 2 MUL ALUS and they require 3 execute cycles, whereas the rest of the ALUS take 1 cycle to execute. LOAD MUL MUL STORE XOR LOAD R1, R2, #100 MUL R2, R1, R3 MUL R1, R1, R2 STORE R1, R2, #200 XOR R2, R1, R3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2. Assume a full-bypass circuit. Draw the pipeline chart showing all the bypass flow and register access flow on the diagram, for the following MIPS code sequence. Assume there are 2 MUL ALUS and they require 3 execute cycles, whereas the rest of the ALUS take 1 cycle to execute. LOAD MUL MUL STORE XOR LOAD R1, R2, #100 MUL R2, R1, R3 MUL R1, R1, R2 STORE R1, R2, #200 XOR R2, R1, R3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18