6. Based on 1K-8 RAM with address lines Ag-A, and one 2-to-4 decode (with 2 inputs...

Transcribed Image Text:

6. Based on 1K-8 RAM with address lines Ag-A, and one 2-to-4 decode (with 2 inputs A and B, and 4 outputs Yo-Ya), two memory devices are implemented in Fig. 6. Let the notation "" denote that the b-bit data buses from memories are combined to form a 26-bit data bus. Let the notation "+" denote that the b-bit data buses from memories are connected together and the data bus for the expanded memory remain b bits wide. For example the concatenation of (9)||(10) is a 16- bit data bus, where 8 bits are from memory device #1 and other 8 bits are form memory device #2. The combination of (9)+(10) is a 8-bit data bus, and only one memory device (#1 or #2) is active at a time for this connection. Please use this way to describe the RAM in the following questions. (a) A 2K-16 RAM in Fig. 6(a) is realized by connecting A and B. What are the inputs and the outputs of this RAM? (4%) (b) About the 2K-16 RAM in Fig. 6(a), if using pin (1) as Aso, what is the address 1027 (decimal value) located in which IC? (4%) (c) A 4K-8 RAM in Fig. 6(b) is realized by using A and B as two extra address lines. What are the inputs and the outputs of this RAM? (4 %) (d) About the 4K-8 RAM in Fig. 6(c), if using B (pin (2)) and A (pin (1)) as An and A, respectively, what is the address 2048 (decimal value) located in which IC? (4%) Expansion of memory device (3) by using decoder (1) A 2 2 (2) In Address Ag-As 2-40-4 decoder Input (4) Data Yo p-x p-y Y (5) Input Dita Data Input (6) Data (7) RAW N 8 8 10 IK X8 RAM CS RW #1 IK X8 RAM V Ag-As CS RW #2 IK X8 RAM, V Ag-Ay CS #3 1K x 8 RAM V Ag-A CS RAW #4 (a) Output Data Output Dala Output Data Output Dala (8) (9) (10) (11) Address (4) A-A 2-to-4 decoder (1) A-2 (2) B-2 (5) Data (3) D Input (8) (6) Input Data Y Input (7) Data Fig. 6: (a) 2K-16 RAM (b) 4K-8 RAM. 2 RW X V IK 18 RAM CS RW #1 V Ag-Au CS RW #2 IK X8 RAM (b) V Ag-A CS RW #3 V IK X8 RAM V Ag-A CS RW #4 IK X8 RAM Output Data Output Data Output Data Output Data (9) (10) (11) (12) 6. Based on 1K-8 RAM with address lines Ag-A, and one 2-to-4 decode (with 2 inputs A and B, and 4 outputs Yo-Ya), two memory devices are implemented in Fig. 6. Let the notation "" denote that the b-bit data buses from memories are combined to form a 26-bit data bus. Let the notation "+" denote that the b-bit data buses from memories are connected together and the data bus for the expanded memory remain b bits wide. For example the concatenation of (9)||(10) is a 16- bit data bus, where 8 bits are from memory device #1 and other 8 bits are form memory device #2. The combination of (9)+(10) is a 8-bit data bus, and only one memory device (#1 or #2) is active at a time for this connection. Please use this way to describe the RAM in the following questions. (a) A 2K-16 RAM in Fig. 6(a) is realized by connecting A and B. What are the inputs and the outputs of this RAM? (4%) (b) About the 2K-16 RAM in Fig. 6(a), if using pin (1) as Aso, what is the address 1027 (decimal value) located in which IC? (4%) (c) A 4K-8 RAM in Fig. 6(b) is realized by using A and B as two extra address lines. What are the inputs and the outputs of this RAM? (4 %) (d) About the 4K-8 RAM in Fig. 6(c), if using B (pin (2)) and A (pin (1)) as An and A, respectively, what is the address 2048 (decimal value) located in which IC? (4%) Expansion of memory device (3) by using decoder (1) A 2 2 (2) In Address Ag-As 2-40-4 decoder Input (4) Data Yo p-x p-y Y (5) Input Dita Data Input (6) Data (7) RAW N 8 8 10 IK X8 RAM CS RW #1 IK X8 RAM V Ag-As CS RW #2 IK X8 RAM, V Ag-Ay CS #3 1K x 8 RAM V Ag-A CS RAW #4 (a) Output Data Output Dala Output Data Output Dala (8) (9) (10) (11) Address (4) A-A 2-to-4 decoder (1) A-2 (2) B-2 (5) Data (3) D Input (8) (6) Input Data Y Input (7) Data Fig. 6: (a) 2K-16 RAM (b) 4K-8 RAM. 2 RW X V IK 18 RAM CS RW #1 V Ag-Au CS RW #2 IK X8 RAM (b) V Ag-A CS RW #3 V IK X8 RAM V Ag-A CS RW #4 IK X8 RAM Output Data Output Data Output Data Output Data (9) (10) (11) (12)