4. [8 points] We would like to allow RISC-V (RV321/RV641) to support indexed indirect addressing. We...

 

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4. [8 points] We would like to allow RISC-V (RV321/RV641) to support indexed indirect addressing. We want to support load and store instructions of the type lw x8, (x7,x6), which would generate a memory address by taking x6, multiplying by the size of the memory access (in this case, w refers to a 4-byte word, so it would multiply by 4), and adding it to x7 to get the memory address to use. (a) What kinds of operations (in a high level language) would this addressing mode be most useful for? Provide examples. (b) What existing instruction sequence could this replace? (c) How might you modify the existing load/store instructions to support this addressing mode? Could you include a displacement with this addressing mode? Explain why or why not, and how big if you are able to include one. 4. [8 points] We would like to allow RISC-V (RV321/RV641) to support indexed indirect addressing. We want to support load and store instructions of the type lw x8, (x7,x6), which would generate a memory address by taking x6, multiplying by the size of the memory access (in this case, w refers to a 4-byte word, so it would multiply by 4), and adding it to x7 to get the memory address to use. (a) What kinds of operations (in a high level language) would this addressing mode be most useful for? Provide examples. (b) What existing instruction sequence could this replace? (c) How might you modify the existing load/store instructions to support this addressing mode? Could you include a displacement with this addressing mode? Explain why or why not, and how big if you are able to include one.

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a This addressing mode would be most useful for operations involving arrays or data structures where ... View the full answer