Recall that we have implemented an adder/subtractor/multiplier, but we never discussed the divider. One way to...
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Recall that we have implemented an adder/subtractor/multiplier, but we never discussed the divider. One way to implement division is through software, using repeated subtraction as you did custom problem #2. Another way to implement division is in hardware, by using a finite state machine (FSM). The state-transition-diagram below describes a FSM that outputs the results of integer division by 2. The input is the dividend in binary. The FSM has two outputs, one is the current remainder (denoted with an R in front of it in the diagram below); the other is the quotient in binary. The FSM accepts the binary dividend one bit at a time (so it can work for any width #), most significant bit first, and generates the quotient one bit at a time, again, most significant bit first. 0 start RO, O 0 RO, 1 1 1 0 0 R1,0 1 R1, 1 1 a. Create the "present state/ next state" truth table for the above state-transition-diagram You will need to create binary values for the states b. Generate the "Next State Function" at the gate level using a PLA. c. Create the "output function" truth table for the above state-transition-diagram. d. Generate the "output function" at the gate level using a PLA. Recall that we have implemented an adder/subtractor/multiplier, but we never discussed the divider. One way to implement division is through software, using repeated subtraction as you did custom problem #2. Another way to implement division is in hardware, by using a finite state machine (FSM). The state-transition-diagram below describes a FSM that outputs the results of integer division by 2. The input is the dividend in binary. The FSM has two outputs, one is the current remainder (denoted with an R in front of it in the diagram below); the other is the quotient in binary. The FSM accepts the binary dividend one bit at a time (so it can work for any width #), most significant bit first, and generates the quotient one bit at a time, again, most significant bit first. 0 start RO, O 0 RO, 1 1 1 0 0 R1,0 1 R1, 1 1 a. Create the "present state/ next state" truth table for the above state-transition-diagram You will need to create binary values for the states b. Generate the "Next State Function" at the gate level using a PLA. c. Create the "output function" truth table for the above state-transition-diagram. d. Generate the "output function" at the gate level using a PLA.
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To create the present statenext state truth table we need to encode each state with a binary value In the statetransition diagram there are four state... View the full answer
Related Book For
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
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