The following diagram shows a logic circuit for a 4-bit adder/subtractor that accepts two 8-bit numbers...

 

Transcribed Image Text:

The following diagram shows a logic circuit for a 4-bit adder/subtractor that accepts two 8-bit numbers (A7A6 A5A4A3A3AAA and B7 B6 B3 B4B3BBB) and add or subtract them based on the value of Add/Sub input. Cout A7 B7 FA S7 A6 B6 FA S6 A5 B5 FA S5 A4 B4 FA S4 A3 B3 FA $3 A2 B2 FA S2 A1 B1 FA K FA $1 SO The circuit is composed of XOR gates, and full adders. 1. Write dataflow model for full adder. 2. Write VHDL testbenches for full adder to prove its correct functionality. 3. Implement a VHDL structural model of the circuit shown above. Your structural model should use one component you designed in part 1: full adder. 4. Write a VHDL testbench for your complete design and simulate your design to show it successfully Add/Subtract two unsigned numbers. O The following diagram shows a logic circuit for a 4-bit adder/subtractor that accepts two 8-bit numbers (A7A6 A5A4A3A3AAA and B7 B6 B3 B4B3BBB) and add or subtract them based on the value of Add/Sub input. Cout A7 B7 FA S7 A6 B6 FA S6 A5 B5 FA S5 A4 B4 FA S4 A3 B3 FA $3 A2 B2 FA S2 A1 B1 FA K FA $1 SO The circuit is composed of XOR gates, and full adders. 1. Write dataflow model for full adder. 2. Write VHDL testbenches for full adder to prove its correct functionality. 3. Implement a VHDL structural model of the circuit shown above. Your structural model should use one component you designed in part 1: full adder. 4. Write a VHDL testbench for your complete design and simulate your design to show it successfully Add/Subtract two unsigned numbers. O

Answer rating: 100% (QA)

1 vhdl library IEEE use IEEESTDLOGIC1164ALL entity fulladderd... View the full answer