The rise and fall times for a CMOS inverter driving a load capacitor are given by...
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The rise and fall times for a CMOS inverter driving a load capacitor are given by C(V₁ + VTp) C In VDD + VOH-2V₁ - 2VTP VDD -VOH KP(VDD - Vi-VTp)² Kp(VDD - Vi - VTp) C(VDD – Vi+Vĩn) C Kn (Vi-VTn)² Kn(Vi-VTn) 2 Trise = Tfall = + = + In = 1.8V, VTn 0.4V, VTP = 0.45V, n 270cm²/Vs, and You are given that VDD Hp = 130cm²/Vs. The n and p channel transistors have the same channel length and gate oxide capacitance per unit area. What should be the ratio of widths of n and p channel transistors such that the time taken to charge the output from 0V to VDD - VTp with the input voltage VTn is the same as the time taken to discharge the output from VDD to VTn with the input voltage VDD - VTp. 2(Vi-VTn) - VOL VOL = = The rise and fall times for a CMOS inverter driving a load capacitor are given by C(V₁ + VTp) C In VDD + VOH-2V₁ - 2VTP VDD -VOH KP(VDD - Vi-VTp)² Kp(VDD - Vi - VTp) C(VDD – Vi+Vĩn) C Kn (Vi-VTn)² Kn(Vi-VTn) 2 Trise = Tfall = + = + In = 1.8V, VTn 0.4V, VTP = 0.45V, n 270cm²/Vs, and You are given that VDD Hp = 130cm²/Vs. The n and p channel transistors have the same channel length and gate oxide capacitance per unit area. What should be the ratio of widths of n and p channel transistors such that the time taken to charge the output from 0V to VDD - VTp with the input voltage VTn is the same as the time taken to discharge the output from VDD to VTn with the input voltage VDD - VTp. 2(Vi-VTn) - VOL VOL = =
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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