(a) Design the circuit shown in Figure P11.16 such that \(v_{O}=\) \(v_{C 1}-v_{C 2}=1 \mathrm{~V}\) when \(v_{1}=-5 \mathrm{mV}\) and \(v_{2}=+5 \mathrm{mV}\). The transistor parameters are \(\beta=180, V_{B E}(\) on \()=0.7 \mathrm{~V}\), and \(V_{A}=\infty\).

(b) Using the results of part (a), determine the maximum common-mode input voltage.

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V+= 10 V Re RC "C1 C2 Q2 10=2 mA V-=-10 V Figure P11.16