Consider the simple MOS op-amp circuit shown in Figure P13.1. The bias current is \(I_{Q}=200 \mu \mathrm{A}\). Transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=\) \(40 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.4 \mathrm{~V}, V_{T P}=-0.4 \mathrm{~V}\), and \(\lambda_{n}=\lambda_{p}=0\). The width-tolength ratio \((W / L)\) for \(M_{1}\) and \(M_{2}\) is 20 and for \(M_{3}\) is 40 .

(a) Design the circuit such that \(I_{D 3}=200 \mu \mathrm{A}\) and \(v_{o}=0\) when \(v_{1}=v_{2}=0\).

(b) Find the smallsignal voltage gains (i) \(A_{d}=v_{o 1} / v_{d}\) and (ii) \(A_{2}=v_{o} / v_{o 1}\).

(c) Determine the overall small-signal voltage gain \(A=v_{o} / v_{d}\).

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V+=3 V Rp1 Vol ww M M2 Figure P13.1 V-=-3 V Rpl M3 www Rp2