Design the circuit in Figure 13.2 such that the maximum power dissipated in the circuit is \(15 \mathrm{~mW}\) and such that the common-mode input voltage is in the range \(-3 \leq v_{C M} \leq 3  \mathrm{~V}\). Using a computer simulation, adjust the value of \(R_{3}\) such that the output voltage is zero for zero input signal voltages.

Transcribed Image Text:

www RC Vol V = 3 V Q2 2 Rei V=-3 V Figure P13.2 Re Q3 RE= 10.5