For the cascode circuit in Figure 4.51 in the text, the transistor parameters are: \(V_{T N 1}=V_{T N 2}=1 \mathrm{~V}, K_{n 1}=K_{n 2}=2 \mathrm{~mA} / \mathrm{V}^{2}\), and \(\lambda_{1}=\lambda_{2}=0\).

(a) Let \(R_{S}=1.2 \mathrm{k} \Omega\) and \(R_{1}+R_{2}+R_{3}=500 \mathrm{k} \Omega\). Design the circuit such that \(I_{D Q}=3 \mathrm{~mA}\) and \(V_{D S Q 1}=V_{D S Q 2}=2.5 \mathrm{~V}\).

(b) Determine the small-signal voltage gain \(A_{v}=v_{o} / v_{i}\).

Figure 4.51:-

Transcribed Image Text:

Vi +1 CG ww V+= 5 V R = 95.4 RD=2.5 k Cc HH ww R = 150 R3= 54.6 M M Rs = Cs 10 V-=-5 V Figure 4.51 NMOS cascode circuit