The supply voltages to the cascode circuit in Figure 4.51 in the text are changed to \(V^{+}=10 \mathrm{~V}\) and \(V^{-}=-10 \mathrm{~V}\). The transistor parameters are: \(K_{n 1}=K_{n 2}=4 \mathrm{~mA} / \mathrm{V}^{2}, V_{T N 1}=V_{T N 2}=1.5 \mathrm{~V}\), and \(\lambda_{1}=\lambda_{2}=0\).

(a) Let \(R_{S}=2 \mathrm{k} \Omega\), and assume the current in the bias resistors is \(0.1 \mathrm{~mA}\). Design the circuit such that \(I_{D Q}=5 \mathrm{~mA}\) and \(V_{D S Q 1}=V_{D S Q 2}=3.5 \mathrm{~V}\).

(b) Determine the resulting small-signal voltage gain.

Transcribed Image Text:

Vi +1 CG ww V+= 5 V R = 95.4 RD=2.5 k Cc HH ww R = 150 R3= 54.6 M M Rs = Cs 10 V-=-5 V Figure 4.51 NMOS cascode circuit