In this problem you are to compare reading a file using a single-threaded file server and a multithreaded server. It takes 12 msec to get a request for work, dispatch it, and do the rest of the...

Consider the following two-dimensional array: int X[64][64]; Suppose that a system has four page frames and each frame is 128 words (an integer occupies one word). Programs that manipulate the X...

Name one advantage of hard links over symbolic links and one advantage of symbolic links over hard links.

Explain how the system can recover from the deadlock in previous problem using (a) Recovery through preemption. (b) Recovery through rollback. (c) Recovery through killing processes.

Explain how the x86's four protection rings can be used to support virtualization.

In every process' entry in the task structure, the PID of the parent is stored. Why?

Revise the ER diagram drawn in the previous exercise to include the following mandatory attributes: CLIENT- ID number, name, address (city, state, zip), phone number(s), birthdate; AGENT - agent...

Distinguish between a simple attribute, a single-valued attribute, a composite attribute, a multi-valued attribute, and a complex attribute. Develop an example similar to Figure 2.3 that illustrates...

What is information preservation and why is it important?

Transform the look-across notation of the Presentation Layer ER diagram in Exercise 7 to a Design-Specific ER diagram that makes use of the (min, max) notation for specifying the structural...

Identify the superkeys, candidate key(s), and the primary key for the following relation instance of the STU-CLASS relation schema. Student Number Student ACCOUNTING STEDRY ANTHROPOLOGY AP150 MWE9 5...

Consider the following relation instance of the CAR relation schema: a. What is the minimal cover of functional dependencies that exists in CAR? b. What is (are) the candidate key(s) of CAR? c. If...

Consider the relation instance STUDENT (Major, Stu_id, Activity, Name, Phone) a. Identify all multi-valued dependencies in STUDENT. b. Describe insertion, deletion, and update anomalies that...

Early examples of CISC and RISC design are the VAX 11/780 and the IBM RS/6000, respectively. Using a typical benchmark program, the following machine characteristics result: The final column shows...

A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.

You must have completed Exercise 11 of Chapter 10 before beginning this exercise, and thus have used the SQL Data Definition Language to populate the tables for the three relations COMPANY, STUDENT,...

Consider the example in Section 2.5 for the calculation of average CPI and MIPS rate, which yielded the result of CPI = 2.24 and MIPS rate = 178. Now assume that the program can be executed in eight...

How is the syndrome for the Hamming code interpreted?

Suppose an 8-bit data word stored in memory is 11000010. Using the Hamming algorithm, determine what check bits would be stored in memory with the data word. Show how you got your answer.

Consider a disk with N tracks numbered from 0 to (N - 1) and assume that requested sectors are distributed randomly and evenly over the disk. We want to calculate the average number of tracks...

Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. a. Assume that interrupt processing takes about 100 s...

Find the following differences using twos complement arithmetic: a. 111000 -110011 b. 11001100 - 101110 c. 111100001111 -110011110011 d. 11000011 -11101000

Add columns to Table 9.1 for sign magnitude and ones complement.

In Section 9.3, the twos complement operation is defined as follows. To find the twos complement of X, take the Boolean complement of each bit of X, and then add 1. a. Show that the following is an...

Consider the twos complement addition of two n-bit numbers: zn-1zn-2 ... z0 = xn-1xn-2 ... x0 + yn-1yn-2 ... y0 Assume that bitwise addition is performed with a carry bit ci generated by the addition...

What are the typical elements of a machine instruction?

What is the difference between big endian and little endian?

List and briefly explain five important instruction set design issues.

What is the relationship between the IRA character code and the packed decimal representation?

What is the difference between an arithmetic shift and a logical shift?

Why are transfer of control instructions needed?

Suppose a stack is to be used by the processor to manage procedure calls and returns. Can the program counter be eliminated by using the top of the stack as a program counter? Discuss.

Suppose that two registers contain the following hexadecimal values: AB0890C2, 4598EE50.What is the result of adding them using MMX instructions: a. For packed byte b. For packed word Assume...

Convert the following formulas from reverse Polish to infix: a. AB + C + D b. AB/CD/ + c. ABCDE + / d. ABCDE + F/ + G - H/ +

Show the calculation of the expression in Figure 10.17, using a presentation similar to Figure 10.16.

Redraw the little-endian layout in Figure 10.18 so that the bytes appear as numbered in the big-endian layout. That is, show memory in 64-bit rows, with the bytes listed left to right, top to bottom.

For the following data structures, draw the big-endian and little-endian layouts, using the format of Figure 10.18, and comment on the results. a. struct { double i; //0x1112131415161718 } s1; b....

The IBM Power architecture specification does not dictate how a processor should implement little-endian mode. It specifies only the view of memory a processor must have when operating in...

Write a small program to determine the endianness of machine and report the results. Run the program on a computer available to you and turn in the output.

Most, but not all, processors use big- or little-endian bit ordering within a byte that is consistent with big- or little-endian ordering of bytes within a multibyte scalar. Let us consider the...

A given microprocessor has words of 1 byte. What is the smallest and largest integer that can be represented in the following representations: a. Unsigned b. Sign-magnitude c. Ones complement d. Twos...

Many processors provide logic for performing arithmetic on packed decimal numbers. Although the rules for decimal arithmetic are similar to those for binary operations, the decimal results may...

Many instruction sets contain the instruction NOOP, meaning no operation, which has no effect on the processor state other than incrementing the program counter. Suggest some uses of this instruction.

In Section 10.4, it was stated that both an arithmetic left shift and a logical left shift correspond to a multiplication by 2 when there is no overflow, and if overflow occurs, arithmetic and...

What facts go into determining the use of the addressing bits of an instruction?

What are the advantages and disadvantages of using a variable-length instruction format?

Briefly define displacement addressing.

What is the advantage of auto indexing?

What is the difference between post indexing and pre indexing?

The x86 includes the following instruction: IMUL op1, op2, immediate This instruction multiplies op2, which may be either register or memory, by the immediate operand value, and places the result in...

Assume a stack-oriented processor that includes the stack operations PUSH and POP. Arithmetic operations automatically involve the top one or two stack elements. Begin with an empty stack. What stack...

Why was IBM's decision to move from 36 bits to 32 bits per word wrenching, and to whom?

Assume an instruction set that uses a fixed 16-bit instruction length. Operand specifiers are 6 bits in length. There are K two-operand instructions and L zero-operand instructions. What is the...

Design a variable-length opcode to allow all of the following to be encoded in a 36-bit instruction: Instructions with two 15-bit addresses and one 3-bit register number Instructions with one...

Is there any possible justification for an instruction with two opcodes?

In [COOK82], the author proposes that the PC-relative addressing modes be eliminated in favor of other modes, such as the use of a stack. What is the disadvantage of this proposal?

What general roles are performed by processor registers?

What is the function of condition codes?

What is a program status word?

Why is a two-stage instruction pipeline unlikely to cut the instruction cycle time in half, compared with the use of no pipeline?

List and briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions.

How are history bits used for branch prediction?

A non pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline...

Consider an instruction sequence of length n that is streaming through the instruction pipeline. Let p be the probability of encountering a conditional or unconditional branch instruction, and let q...

A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles....

Assume a pipeline with four stages: fetch instruction (FI), decode instruction and calculate addresses (DA), fetch operand (FO), and execute (EX). Draw a diagram similar to Figures 12.10 for a...

Consider the timing diagram of Figures 12.10. Assume that there is only a two-stage pipeline (fetch, execute). Redraw the diagram to show how many time units are now needed for four instructions....

What are some typical distinguishing characteristics of RISC organization?

Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.

If a circular register buffer is used to handle local variables for nested procedures, describe two approaches for handling global variables.

Add entries for the following processors to Table 13.7: Table 13.7 Characteristics of Some Processors a. Pentium II b. ARM Number of Number Max instruction Number of Load/store Max Max bits for...

What is the essential characteristic of the superscalar approach to processor design?

What is the difference between the superscalar and super pipelined approaches?

Briefly define the following terms: True data dependency Procedural dependency Resource conflicts Output dependency Ant dependency

What is the distinction between instruction-level parallelism and machine parallelism?

List and briefly define three types of superscalar instruction issue policies.

What is register renaming and what is its purpose?

When out-of-order completion is used in a superscalar processor, resumption of execution after interrupt processing is complicated, because the exceptional condition may have been detected as an...

a. Identify the write-read, write-write, and read-write dependencies in the following instruction sequence: b. Rename the registers from part (a) to prevent dependency problems. Identify references...

Can you foresee any problem with the write-once cache approach on bus-based multiprocessors? If so, suggest a solution.

Convert the following hexadecimal numbers to their binary equivalents: a. E b. 1C c. A64 d. 1F.C e. 239.4

Equations (19.1) and (19.2) define the representation of numbers in base 10 and base 2, respectively. In general, for the representation in base g of = {... x2x1x0 x-1x-2x-3....}, the value of X is...

Perform the indicated base conversions: a. 548 to base 5 b. 3124 to base 7 c. 5206 to base 7 d. 122123 to base 9

Design a 2 32 decoder using four 3 8 decoders (with enable inputs) and one 2 4 decoder.

Simplify the following expressions according to the commutative law: a. b. A B + A C + B A c. (L M N)(A B)(C D E)(M N L) d. F (K + R) + S V + W + V S + W + (R + K) F A.B + B.A + C.D.E + C.DE + E.T.D

List and briefly define four different kinds of assembly language statements.

What is the difference between a one-pass assembler and a two-pass assembler?

Section B.1 includes a C program that calculates the greatest common divisor of two integers. a. Describe the algorithm in words and show how the program does implement the Euclid algorithm approach...

a. A 2-pass assembler can handle future symbols and an instruction can therefore use a future symbol as an operand. This is not always true for directives. The EQU directive, for example, cannot use...

How would the following program fare against Imp? Loop COPY #0, -1 JUMP -1 Remember that instruction execution alternates between the two opposing programs.

(a) Who is subject to FISMA? (b) Distinguish between certification and accreditation in FISMA. (c) Why has FISMA been criticized?

Illustrate the UML Diagram for exercise 7.16. Your UML design should observe the following requirements: a. The student should have the ability to compute his/her GPA and add or drop majors and...

Consider the ER diagram shown in Figure 7.21 for part of a BANK database. Each bank can have multiple branches, and each branch can have multiple accounts and loans. (a) List the strong (nonweak)...

Consider the following relation: R (Doctor#, Patient#, Date, Diagnosis, Treat_code, Charge) In this relation, a tuple describes a visit of a patient to a doctor along with a treatment code and daily...

Consider the relation: BOOK (Book_Name, Author, Edition, Year) with the data: a. Based on a common-sense understanding of the above data, what are the possible candidate keys of this relation? b....

Consider the relation R, which has attributes that hold schedules of courses and sections at a university; R = {CourseNo, SecNo, OfferingDept, CreditHours, CourseLevel, InstructorSSN, Semester, Year,...

Suppose Bob joins a BitTorrent torrent, but he does not want to upload any data to any other peers (so called free-riding). a. Bob claims that he can receive a complete copy of the file that is...

Write a simple TCP program for a server that accepts lines of input from a client and prints the lines onto the server's standard output. (You can do this by modifying the TCPServer java program in...

Host A and B are communicating over a TCP connection, and Host B has already received from A all bytes up through byte 126. Suppose Host A then sends two segments to Host B back-to-back. The first...

Consider that only a single TCP (Reno) connection uses one 10Mbps link which does not buffer any data. Suppose that this link is the only congested link between the sending and receiving hosts....