Calculate the small-signal model parameters of the device shown in Fig. 2.74, including g_m, g_mb, r_o, C_gs, C_gd, C_sb, and C_db.

Fig. 2.74

 

Assume the transistor is biased at a drain-source voltage of 2 V and a drain current of 20 μA. Use the process parameters that are specified in Table 2.4. Assume V_SB = 1 V.

Table 2.4

Transcribed Image Text:

1 μm . -1 μ 1 μm 10 μ Source: Gate Drain ν Value Value p-Channel Transistor n-Channel Parameter Symbol Transistor Units Substrate doping Gate oxide thickness NA, Np 5 x 1015 4 x 1016 Atoms/cm tox 80 80 Metal-silicon work function Фия -0.6 -0.1 Channel mobility 450 150 cm²/V-s Minimum drawn channel Ldran 0.4 0.4 um length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate width 0.15 0.18 х, La μη 0.09 0.09 Col 0.35 0.35 fF/um Threshold adjust implant (box dist) impurity type effective depth Xị 0.16 0.16 um effective surface 4 x 1016 3 x 1016 Atoms/cm concentration Nominal threshold voltage Polysilicon gate doping concentration Poly gate sheet resistance Source, drain-bulk junction capacitances (zero bias) Source, drain-bulk junction capacitance grading V, 0.6 -0.8 Napoly 1020 1020 Atoms/cm R, 5 5 0.2 0.4 fF/µm? п 0.5 0.4 coefficient С уюо 1.2 Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading coefficient 2.4 fF/um п 0.4 0.3 Source, drain junction built-in potential 0.7 0.7 Qss Surface-state density 10" 10" Atoms/cm? dX4 Channel-length modulation 0.02 0.04 иm/V dVDs parameter