A sequential circuit consists of a PLA and a D flip-flop, as shown in the following diagram.

(a) Complete the timing diagram assuming that the propagation delay for the PLA is in the range 5 to 10 ns and the propagation delay from clock to output of the D flip-flop is 5 to 10 ns. Use cross-hatching on your timing diagram to indicate the intervals in which Q and Z can change, taking the range of propagation delays into account.
(b) Assuming that X always changes at the same time as the falling edge of the clock, what is the maximum setup and hold time specification that the flipflop can have and still maintain proper operation of the circuit?

Transcribed Image Text:

Q lo 1 PLA CLK Q+ CLK + + + ns 40 60 20 80 120