Make a one-hot state assignment for Figure 4-53 and write the next-state and output equations by inspection.
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-HLdl SICM1 Ldd S2 St/Ldu Lds So St'/0 S3 Rdy S'/Ldd CIV -ISh C' Qneg'/0 C' Qneg/Cml K'C'ISh S4 C'ISh S6 S5 KC'ISh CISU CISU FIGURE 4-53: StateGraph for Signed Divider Control Circuit
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S 0 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 1000000 S 1 0100000 ...View the full answer
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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