A simple CMOS op-amp circuit is shown in Figure P13.30 with \(I_{Q}=\) \(100 \mu \mathrm{A}\). The transistor parameters are the same as given in Problem 13.29 except for the width-to-length ratios. The width-to-length ratios are \((W / L)_{1,2}=80,(W / L)_{3}=25\), and \((W / L)_{4}=100\).

(a) The circuit is to be designed such that \(I_{D Q 3}=100 \mu \mathrm{A}, I_{D Q 4}=200 \mu \mathrm{A}\), and \(v_{o}=0\) for \(v_{1}=v_{2}=0\).

(b) Determine the small-signal voltage gains (i) \(A_{d}=v_{o 1} / v_{d}\), (ii) \(A_{2}=v_{o 2} / v_{o 1}\), and (iii) \(A_{3}=v_{o} / v_{o 2}\).

(c) Find the overall small-signal voltage gain \(A=v_{o} / v_{d}\).

Data From Problem 13.29:-

Consider the simple CMOS op-amp circuit in Figure P13.29 biased with \(I_{Q}=200 \mu \mathrm{A}\). The transistor parameters are \(k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=\) \(40 \mu \mathrm{A} / \mathrm{V}^{2}, V_{T N}=0.4 \mathrm{~V}, V_{T P}=-0.4 \mathrm{~V}\), and \(\lambda_{n}=\lambda_{p}=0\). The transistor width-to-length ratios are \((W / L)_{1,2}=20,(W / L)_{3}=50\), and \((W / L)_{4}=40\).

(a) Design the circuit such that \(I_{D 3}=150 \mu \mathrm{A}, I_{D 4}=200 \mu \mathrm{A}\), and \(v_{o}=0\) for \(v_{1}=v_{2}=0\).

(b) Find the small-signal voltage gains (i) \(A_{d}=v_{o 1} / v_{d}\), (ii) \(A_{2}=v_{o 2} / v_{o 1}\), and (iii) \(A_{3}=v_{o} / v_{o 2}\).

(c) Determine the overall smallsignal voltage gain \(A=v_{o} / v_{d}\).

Transcribed Image Text:

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