Consider the circuit of Figure P6-28 (cdot R_{1}=R_{2}=1) (mathrm{M} Omega, C_{1}=C_{2}=1 mu mathrm{F}), and the capacitors have

Question:

Consider the circuit of Figure P6-28 $\cdot R_{1}=R_{2}=1$ $\mathrm{M} \Omega, C_{1}=C_{2}=1 \mu \mathrm{F}$, and the capacitors have zero initial conditions, the output should, in theory, be the same as the input as long as the OP AMPs are not saturated.
(a) Demonstrate that this is true.
(b) Test this in Multisim by inputting a 1 radian/s sine wave into the cascaded OP AMP circuit and plot the input, the output of the first stage, and the output of the second stage. Comment on the results.

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