In the following Verilog process A, B, C, and D are all registers that have a value of 0 at time = 10ns. If E changes from 0 to 1 at time = 20ns, specify the time(s) at which each signal will change and the value to which it will change. List these changes in chronological order.

always
begin
wait(E);
A <= #5 1;
B <= A + 1;
C <= #10 B;
D <= #3 B;
A <= #15 A + 5;
B <= B + 7;
end