Question: An integrated CMOS digital circuit can be represented by the Bode diagram shown in Figure E9.5. (a) Find the gain and phase margins of the

An integrated CMOS digital circuit can be represented by the Bode diagram shown in Figure E9.5.
(a) Find the gain and phase margins of the circuit.
(b) Estimate how much we would need to reduce the system gain (dB) to obtain a phase margin of 60°.

50 40 30 F 320 10 1 kHz 10 kHz 100 kHz 10 MHz -10 -20 -90 180 l kHz 10 kHz 100 kHz MHz 10 MH. Frequency (b)360

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