For each part of this exercise, assume the initial cache and memory state as illustrated in Figure 4.37. Each part of this exercise specifies a sequence of one or more CPU operations of the form:
P#:

[ ]
Where P# designates the CPU (e.g., P0), is the CPU operation (e.g., read or write),

denotes the memory address, and indicates the new word to be assigned on a write operation.
Treat each action below as independently applied to the initial state as given in Figure 4.37. What is the resulting state (i.e., coherence state, tags, and data) of the caches and memory after the given action? Show only the blocks that change, for example, P0.B0: (I, 120, 00 01) indicates that CPU P0's block B0 has the final state of I, tag of 120, and data words 00 and 01. Also, what value is returned by each read operation?
a. P0: read 120
b. P0: write 120

Figure 4.37 Bus-based snooping multiprocessor.
c. P15: write 120 d. P1: read 110
e. P0: write 108 f. P0: write 130 g. P15: write 130

PO P1 P15 BO 100 00 | 10 B1 S 108 00 08 B2M 110 100 30 B3 118 00 10 801100 00 10 81 M 128 00 68 B2110 0010 B3S | 118 | 001 18 BoIS|120100120 B1 S108 00 08 B2110 00 10 B3118 00 1 10 Memory Address Data 100 00 00 108 00 08 110 00 10 118 00 18 120 00 20 128 0028 130 00 30