For a small heat source attached to a large substrate, the spreading resistance associated with multidimensional conduction in the substrate may be approximated by the expression where Ar = As,h/As.sub is the ratio of the heat source area to the substrate area. Consider application of the expression to an in-line array of square chips of width Lh = 5 mm on a side and pitch Sh = 10 mm. The interface between the chips and a large substrate of thermal conductivity ksub = 80 W/m ∙ K is characterized by a thermal contact resistance of Rt,c = 0.5 X 10-4 m2 ∙ K/W.

If a convection heat transfer coefficient of h = 100 W/m2 ∙ K is associated with air flow (T∞ = 15°C) over the chips and substrate, what is the maximum allowable chip power dissipation if the chip temperature is not to exceed Th = 85°C?

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+ 0.043 A; + 0.034 A, 1- 1.410A, + 0.344 A Resp) 12 4k subAh Top view Chip, T Side view Air Substrate Rie