A cache memory may be operated in either a serial or a parallel mode with respect to the main memory. In the serial access mode, the cache is examined for data, and if a miss occurs, the main storage is then accessed. In the parallel access mode, both the cache and the main store are accessed simultaneously. If a hit occurs, the access to the main store is aborted. Assume that the system has a hit ratio h and that the ratio of cache memory access time to main store access time is k (k < 1). Derive an expression for the speedup ratio of both a serial access and a parallel access cache.