Assume the constants shown as follows.

Write code for RISC-V and RV64V. Assume the starting addresses of tiPL, tiPR, clL, clR, and clP are in RtiPL, RtiPR, RclL, RclR, and RclP, respectively. Do not unroll the loop. To facilitate vector addition reductions, assume that we add the following instructions to RV64V: Vector Summation Reduction Single Precision: vsum Fd, Vs This instruction performs a summation reduction on a vector register Vs, writing to the sum into scalar register Fd.

Constants AA,AC,AG,AT CA,CC,CG,CT GA,GC,GG,GT TA,TC,TG,TT A,C,G,T Values 0,1,2,3 4,5,6,7 8,9,10,11 12,13,14,15 0,1,2,3