The signal flow graph together with state variable assignment is shown below:

The condition for complete state controllability and complete observability is:
(a) \(d eq 0\) and \(a, b, c\) can be anything.
(b) \(a eq 0\) and \(b, c, d\) can be anything.
(c) \(b eq 0\) and \(a, c, d\) can be anything.
(d) \(c eq 0\) and \(a, b, d\) can be anything.

ro 1/s a C d 1/s b