Given the system of Figure P9.4:

a. Design the value of K₁, as well as a in the feedback path of the minor loop, to yield a settling time of 4 seconds with 5% overshoot for the step response.

b. Design the value of K to yield a major-loop response with 10% overshoot for a step input.

c. Use MATLAB or any other computer program to simulate the step response to the entire closed-loop system.

d. Add a PI compensator to reduce the major-loop steady-state error to zero and simulate the step response using MATLAB or any other computer program.

Transcribed Image Text:

KL s(s + 2)(s + 5) R(s) + C(s) K s+a FIGURE P9.4