Construct a block description file (bdf) of a register that consists of four D flip-flops using the DFF primitive. From this BDF file, create a block symbol and include it in a new design. The new design will have inputs named D[3..0], TRANSFER (clock input), and Q[3..0]. Determine its operation when the input signals shown in Figure 5-70 are applied. Functionally simulate the register using Quartus to verify your prediction.

Figure 5-70

>0 -1 D-2 D-3 C-4 D-5 Name TRANSFER D[3] -D[2] D[1] -D[0] 0 ps 0 ps 2.0 us 0101 4.0 us 6.0 us 1100 8.0 us 10.0 us 0111 12.0 us 14.0 us 1000 16.0 us 18.0 us