Create an eight-bit PISO shift register. The data in is d[7..0] and the output is q0. The shift-register function is controlled by sh_ld 1sh_ld = 0 to synchronously parallel load and sh_ld = 1 to serial shift). The serial input while shifting should be a constant LOW. The register also should have an active-LOW asynchronous clear (clrn). Simulate (functional) the design.

(a) Use LPM_SHIFTREG. Use any necessary logic gates.

(b) Use an HDL.