Question: How would the staircase waveform appear if the C input to the DAC of Figure 11-3 is open? Assume that the DAC inputs are TTL-compatible.
How would the staircase waveform appear if the C input to the DAC of Figure 11-3 is open? Assume that the DAC inputs are TTL-compatible.
Figure 11-3

Clock Four-bit counter D C B A D/A converter Resolution = 1 V OV VOUT Full scale (input = 1111) Resolution= Input recycled to 0000 step size = 1 V 15 V Time
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An open connection at C will be interpreted as a constant logic 1 by the DAC Thus this will con... View full answer
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