What input address code is required if we want to read the data from register 9 in Figure 12-7?

CS OE A A A A ROW SELECT 0 1 2 3 1-of-4 decoder MSB E COLUMN SELECT 0 1-of-4 decoder 1 2 3 MSB E Row 0 Row 1 Row 2 Row 3 Column 0 Column 1 Column 2 Column 0 Register 0 Register 1 Register 2 Register 3 Column 3 m Column 1 Register 4 v E Register 5 Register 6 Register 7 E Column 2 Register 8 Register 91 Register 10 Register 11 [8] Output buffers Dy Dj Ds Dj Dz D D Do FIGURE 12-7 Architecture of a 16 x 8 ROM. Each register stores one eight-bit word. Column 3 Register 12 Register 13 Register 14 U Register 15