Repeat Problem 9.17 but with the following change in the specification. While w = 1, the output z should have only one pulse; if several pulses occur on c, only the first one should be reproduced on z.

Data From Problem 9.17

Design an asynchronous circuit that meets the following specifications. The circuit has two inputs: a clock input c and a control input w. The output, z, replicates the clock pulses when w = 1; otherwise, z = 0. The pulses appearing on z must be full pulses. Consequently, if c = 1 when w changes from 0 to 1, then the circuit will not produce a partial pulse on z, but will wait until the next clock pulse to generate z = 1. If c = 1 when w changes from 1 to 0, then a full pulse must be generated; that is, z = 1 as long as c = 1. Figure P9.7 illustrates the desired operation.