Exercise 7.10 (Simulation Based on a Global List of Phases). Execute several simulations of a modified circuit created from the circuit structure in Fig. 7.1. The circuit is extended such that additional outputs y2, y3, and y4 are introduced which are connected with the outputs of the gates g20, g11, and g23 in the given order. Practical tasks:

1 Load the TVL system of Exercise 7.7.

2 Extend the behavior by the outputs y2, y3, and y4 as specified in this Exercise.

3 Prepare VTs for the inputs, the internal signals, and the outputs.

4 Execute a forward simulation based on formula (7.52) of [18] that finds the values of the four outputs for the input pattern (x1, x2, x3, x4, x5, x6)

that are equal to either (100010) or (011010). Calculate both the simulation pattern (x, y) and the restricted simulation result (y). Evaluate the simulation result.

5 Execute a backward simulation based on formula (7.53) of [18] that finds the values of the six inputs for the output pattern (y, y2, y3, y4) that are equal to either (1010) or (0101). Calculate both the simulation pattern (x, y) and the restricted simulation result (x). Evaluate the simulation result.

6 Execute a general simulation based on formula (7.54) of [18] that finds the values of the six inputs and four outputs for the pattern (g1, g5, g7)

of the reused internal signals that are equal to either (010) or (101).

Calculate the restricted simulation result (x, y) and evaluate it.