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Consider the following IC distribution and ideal CPI values.

loads: $20\%$ CPI $=4$; stores: $20\%$ CPI $=3$; others: $60\%$ CPI $=1$

Assume that the unified cache is used with miss rate $10\%$ and miss penalty $30$ clock cycles.

$($a$)$ Compute and show the effective CPU$\_$exec time $($considering both hits and misses$).$

CPUexe $=($CPU clock cycles $+$ mem. stall cycles$)*$ CCT

$-$IC $*$ CPI tot#$\_$of$\_$cache$\_$misses $*$ miss$\_$penalty

$-$IC $*$ misses$\_$per$\_$instr.

$-$mem$\_$ref.s$\_$per$\_$instr. $*$ miss$\_$rat

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