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-------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/25/202410:37:53 AM
-- Design Name:
-- Module Name: counter_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01- File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_display is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
digit1 : inout STD_LOGIC_VECTOR (3 downto 0);
digit2 : inout STD_LOGIC_VECTOR (3 downto 0));
end counter_display;
architecture Behavioral of counter_display is
signal count : integer range 0 to 99 :=0;
signal clk_div : integer range 0 to 50000000 :=0;
signal one_sec_clk : STD_LOGIC :='0';
begin
-- Clock Divider for 1-second delay
process(clk)
begin
if rising_edge(clk) then
if clk_div =50000000-1 then
clk_div <=0;
one_sec_clk <= not one_sec_clk;
else
clk_div <= clk_div +1;
end if;
end if;
end process;
-- Counter process
process(one_sec_clk, reset)
begin
if reset ='1' then
count <=0;
elsif rising_edge(one_sec_clk) then
if count =99 then
count <=0;
else
count <= count +1;
end if;
end if;
end process;
--7-segment decoder
process(count)
begin
case count/10 is
when 0=> digit1<="0000"; --0
when 1=> digit1<="0001"; --1
when 2=> digit1<="0010"; --2
when 3=> digit1<="0011"; --3
when 4=> digit1<="0100"; --4
when 5=> digit1<="0101"; --5
when 6=> digit1<="0110"; --6
when 7=> digit1<="0111"; --7
when 8=> digit1<="1000"; --8
when 9=> digit1<="1001"; --9
when others => digit1<="0000"; -- Default to 0
end case;
case count mod 10 is
when 0=> digit2<="0000"; --0
when 1=> digit2<="0001"; --1
when 2=> digit2<="0010"; --2
when 3=> digit2<="0011"; --3
when 4=> digit2<="0100"; --4
when 5=> digit2<="0101"; --5
when 6=> digit2<="0110"; --6
when 7=> digit2<="0111"; --7
when 8=> digit2<="1000"; --8
when 9=> digit2<="1001"; --9
when others => digit2<="0000"; -- Default to 0
end case;
end process;
--7-segment display logic
process(digit1, digit2)
begin
case digit1 is
when "0000"=> seg <="0000001"; --0
when "0001"=> seg <="1001111"; --1
when "0010"=> seg <="0010010"; --2
when "0011"=> seg <="0000110"; --3
when "0100"=> seg <="1001100"; --4
when "0101"=> seg <="0100100"; --5
when "0110"=> seg <="0100000"; --6
when "0111"=> seg <="0001111"; --7
when "1000"=> seg <="0000000"; --8
when "1001"=> seg <="0000100"; --9
when others => seg <="1111111"; -- Error
end case;
-- Add logic for second digit (digit2) if needed
end process;
end Behavioral;
Course: EEL 4740
---a constraint code using this format
## This file is a general .xdc for the Zybo Z7 Rev. B
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
##Clock signal
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33}[get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00-waveform {04}[get_ports { sysclk }];
##Switches
#set_property -dict { PACKAGE_PIN G

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