$(10$ points$)$: The total available memory used by processor is $32MB$ with data width of $16$ bits $($i$.$e$.,2$ bytes$).$ If we divide this memory into $4$ blocks, namely Block$0,$ Block$1,$ Block$2,$ and Block$3,$ as shown below. Draw the logical map $($address space$)$ for each block by filling the below address entries and design an external circuit to generate the individual block enable signals namely CSBlock$0*,$ CSBlock$1*,$ CSBlock$2*,$ and CSBlock$3*$ where all chip selects are active low signals