$12\mathrm{.}14\mathrm{.}16$

IF$=250$ps

ID$=350$ps

EX$=150$ps

MEM$=300$ps

WB$=200$ps

ALU$/$Logic$=45\%$

Jump$/$Branch$=20\%$

Load$=20\%$

Store$=15\%$

a$.$What is the clock cycle time time in a pipelined and non$-$pipelined processor

b$.$ What is the total latency of an$$lw$$instruction in a pipelined and non$-$pipelined processor

c$.$ Which stage would you split and what is the new clock cycle time of the processor?

d$.$ Assuming there are no stalls or hazards, what is the utilization of the data memory

e$.$ Assuming there are no stalls or hazards, what is the utilization of the write$-$register port of the "Registers" unit?