$1.(25\text{'})$ Combinational Circuit Design in Verilog: $1).$ Using case statement, design an $8-$function ALU

that takes $4-$bit inputs a and $b,$ and a $3-$bit signal select and gives a $5-$bit output out, as shown in Figure $1.$

The MSB of out $($i$.$e$.$ out$[4])$ is used to store the Carryout flag for addition $(a+b).$ The ALU implements the

following functions based on the $3-$bit input select. Ignore any overflow or underflow. Also sketch the block

diagram of your design, and mark the names $($module name, inputs$/$outputs names$).$

$.$ Write a testbench file to test two sample patterns: $($each pattern lasts for $10ns)$:

i$).$ Select $=010,a=1101,b=0110,$

ii$).$ Select $=111,a=0101,b=1110.$