$1\mathrm{.}2$ The program execution of Figure $1\mathrm{.}4$ is described in the text using six steps. Expand this

description to show the use of the MAR and MBR$.$

$1\mathrm{.}3$ Consider a hypothetical $32-$bit microprocessor having $32-$bit instructions composed of two

fields. The first byte contains the opcode and the remainder an immediate operand or an

operand address.

a$.$ What is the maximum directly addressable memory capacity $($in bytes$)?$

b$.$ Discuss the impact on the system speed if the microprocessor bus has

$1.$ a $32-$bit local address bus and a $16-$bit local data bus, or

$2.$ a $16-$bit local address bus and a $16-$bit local data bus.

c$.$ How many bits are needed for the program counter and the instruction register?

$1\mathrm{.}5$ Consider a $32-$bit microprocessor $,$ with a $16-$bit external data bus, driven by an $8-$MHz input

clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four

input clock cycles. What is the maximum data transfer rate across the bus that this

microprocessor can sustain in bytes$/$s$?$ To increase its performance, would it be better to make

its external data bus $32$ bits or to double the external clock frequency supplied to the

microprocessor? State any other assumptions you make and explain. Hint: Determine the

number of bytes that can be transferred per bus cycle.

$1\mathrm{.}7$ In virtually all systems that include DMA modules, DMA access to main memory is given

higher priority than processor access to main memory. Why?

$1\mathrm{.}8$ A DMA module is transferring characters to main memory from an external device

transmitting at $9600$ bits per second $($bps$).$ The processor can fetch instructions at the rate of $1$

million instructions per second. By how much will the processor be slowed down due to the

DMA activity?