$1.4\mathrm{.}22[5]<4\mathrm{.}6>$ Consider the fragment of MIPS assembly below:

sd $s$5,12($$s$3)$

Id $s$5,8($$s$3)$

sub $s$4,$ $s$2,$ $s$1$

beqz $s$4,$ label

add $s$2,$ $s$0,$ $s$1$

sub $s$2,$ $s$6,$ $s$1$

Suppose we modify the pipeline so that it has only one memory $($that

handles both instructions and data$).$ In this case, there will be a

structural hazard every time a program needs to fetch an instruction

during the same cycle in which another instruction accesses data.

$$

$4\mathrm{.}22\mathrm{.}1[5]<4\mathrm{.}6>$ Draw a pipeline diagram to show were the code

above will stall.