1. A designer has two crystal oscillators available: one at 71 MHz and one at 93 MHz. He/she needs a system clock at a frequency of 8.3 MHz, or as close as possible to 8.3 MHz. A frequency divider circuit such as those discussed in class will be used to get the desired frequency from one of the crystal oscillators. SHOW WORK REASONING: NOT JUST THE ANSWER a) Which crystal oscillator should be used? b) What frequency division factor will be used? c) How many bits are needed for the counter? d) What will the actual frequency of the divider output be? 2. A frequency divider circuit is to be designed that divides the frequency of the input clock by a factor 20. How many bits are needed for the counter? Show reasoning. 3. A divide by 12 frequency divider circuit is being designed. It will take on the form of the diagram below. The 4-bit counter with synchronous load and reset inputs is identical to that of CLASSEX 25; see that for a table of operation if you need to. A duty cycle of 50% is desired. LOAD LOAD COMBINATIONAL LOGIC RESET RESET 4-bit binary counter with synchronous RESET and LOAD CLOCK CLK a) Determine how the 4 parallel data inputs D3 through Do should be connected. Show the connections on the diagram and show below how you determined what they should be. Continued 1. A designer has two crystal oscillators available: one at 71 MHz and one at 93 MHz. He/she needs a system clock at a frequency of 8.3 MHz, or as close as possible to 8.3 MHz. A frequency divider circuit such as those discussed in class will be used to get the desired frequency from one of the crystal oscillators. SHOW WORK REASONING: NOT JUST THE ANSWER a) Which crystal oscillator should be used? b) What frequency division factor will be used? c) How many bits are needed for the counter? d) What will the actual frequency of the divider output be? 2. A frequency divider circuit is to be designed that divides the frequency of the input clock by a factor 20. How many bits are needed for the counter? Show reasoning. 3. A divide by 12 frequency divider circuit is being designed. It will take on the form of the diagram below. The 4-bit counter with synchronous load and reset inputs is identical to that of CLASSEX 25; see that for a table of operation if you need to. A duty cycle of 50% is desired. LOAD LOAD COMBINATIONAL LOGIC RESET RESET 4-bit binary counter with synchronous RESET and LOAD CLOCK CLK a) Determine how the 4 parallel data inputs D3 through Do should be connected. Show the connections on the diagram and show below how you determined what they should be. Continued