1. A hypothetical processor has 6 stages of a pipeline as shown in figure below. The first row in the figure below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. Operands of a particular operation are fetched from the register file in the 3^rd cycle (i.e. Operand Fetch phase). The memory variable is fetched from memory after the execution of 5^th cycle (i.e. Memory access phase). The contents are written in the register after the execution of 6^th cycle. (10)

1	2	3	4	5	6
Instruction Fetch	Instruction Decode	Operand Fetch	Instruction Execute 1	Memory Access	Register Write back
10ns	15ns	10ns	20ns	15ns	20ns

i. How many cycles are required to implement/execute one instruction on this pipeline?

ii. How many cycles are required to execute 5 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions.

iii. Assume that all necessary bypass circuitry is implemented in this 6 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions?

a) R5 = Load from memory

b) R2 = R5 + R7

iv. Assume that no bypass circuitry is implemented in this 6 stage pipeline. How many cycles will the pipeline stall during the execution of above mentioned two instructions?

v. Assume that all necessary bypass circuitry is implemented in this 6 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions?

a) R5 = R1 + R3

b) R2 = R5 + R7

vi. Assume that no bypass circuitry is implemented in this 6 stage pipeline. How many cycles will the pipeline stall during the execution of above mentioned two instructions?

vii. How much total time (in ns) is required to execute one entire instruction if the six stages were not pipelined?

viii. What is the delay of 1 cycle (in ns) when all the six stages are pipelined?

ix. How much total time (in ns) is required to execute one entire instruction if the six stages are pipelined?(Note that in case of pipeline each stage in all stages are equal to the duration of the stage which is larger one)

x. Below are given two sets of codes. For each of these codes, mention if forwarding circuit can avoid all the stalls in the code?

A. add R1, R2, R3

add R6, R7, R8

add R4, R1, R5

B. Load R1,b

add R2, R1, R3

.

2-Draw a space diagram for a 3-segment pipeline showing the time it take to process 7 tasks