1. (A.2) Compute the effective CPI for RISC-V using Figure A.29 and the table below that shows cycles for different instruction types. Average the instruction frequencies for all benchmarks to obtain the instruction mix. You may assume that all other instructions (for instructions not accounted for by the types in Table A.29) require 3.0 clock cycles each. Figure A29. Table Below (A.10) For the following assume that integer values A,B,C,D,E, and F reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits. a. For each instruction set architecture shown in Figure A.2, how many addresses, or names, appear in each instruction for the code to compute C=A+B, and what is the total code size? b. [15] Some of the instruction set architectures in Figure A.2 destroy operands in the course of computation. This loss of data values from processor internal storage has performance consequences. For each architecture in Figure A.2, write the code sequence to compute: C=A+BD=AEE=CDF=EC In your code, mark each operand that is destroyed during execution and mark each "overhead" instruction that is included just to overcome this loss of data from processor internal storage. What is the total code size, the number of bytes of instructions and data moved to or from memory, the number of overhead instructions, and the number of overhead data bytes for each of your code sequences? Figure A.2 (A. 20) Convert the following C code to RISC V assembly instructions (you can use the mnemonics shown in Figure A.28. For (i=0;i