1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It...

 

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1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It performers a set of arithmetic and logical micro operations on two input buses at every rising edge of CLK input signal. An active high RST input is used to synchronously reset the output signal Y to logical zeros. The output Y must be available at every rising edge of CLK and the latencies for all functions is 1 cycle. Inputs of ALU: CLK, RST, 8-bit unsigned A, 8-bit unsigned B, 4-bit unsigned SEL Output of ALU: 8-bit unsigned Y Function table of ALU is given below: Function SEL Operation Number ] 2 3 4 5 6 7 8 9 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 YA Y<=A+B Y<=A+Bbar YA and B Y<A or B Y<=Axor B Y< Abar Ys=shl A Y<=shr A Y<=0 Go to OpenLane folder Sed -/Openlane Ssudo make mount. Now Openlane docker is started S/flow.tel -design alu-init_design_contig package require openlane 0.9 %prep - design alu %run synthesis Sru_lourplan %run placement Srun_cts The whole functions can be implemented using a single case statement even if it is not an optimal way of doing it. You are free to implement them in your way. You can ignore the carry out in addition operations. run routing Srun magic run_magic_spice_export run magic dre %run lvs run antenna_check. A. (35 Points) Implement the given ALU entity in VHDL language. Provide your VHDL code. (35 Points) Implement the given ALU module in Verilog language. Provide your ende. C. (30 Points) Implement the given ALU using OpenLane Design Flow. Hint: Install OpenLane and Magic tools into your Linux machine as described in the class. Create required design files (alu.v, config.tel and sky130A_sky130_fd_sc_hd_config.tcl) and run the following commands those are also described in the class. Function This command creates an alu folder under /designs folder Copy and modify the design files to this folder same as other example designs flow.tel-interactive Transfer A Addition A plus l's complement of B Logical AND Logical OR Logical XOR Complement A Shift left A Shift right A Transfer 0's Go to this folder Sad -/Openlame/designs/counter/runs/..../results/finishing Run magic Smagic -T sky 130A lef read../../tmp/merged lef def read alu.gds & After completion of flow without any error you can run mugic to see GDSII of your design. Open a new terminal and run the following commands. Make sure nor error is generated throughout the flow. set env(IP SIZING) "absolute" set enviDIE AREA) "0 0 100.0 100.0" In the first part of design, let's make the DIE_AREA is absolute and 100 mx100um and set clock frequency to 200MHz.. You can do it hy setting the following parameters. set enviCLOCK PERIOD) "x" */Openlane/designs/alu/runs/name_of_run/reports/synthesis */Openlane/designs/alu/runs/name_of_run/logs/synthesis Provide the screenshot of GDSII file for designed ALU. Provide synthesis statistics, and STA (setup time and hold time analysis) results. They can be found at the following directories: In the second part, lets change DIE_AREA to 75umx100um and rerun the flow. Provide the GDSII for this run as well. 1. An arithmetic logic unit (ALU) is the center of a central processing unit (CPU). It performers a set of arithmetic and logical micro operations on two input buses at every rising edge of CLK input signal. An active high RST input is used to synchronously reset the output signal Y to logical zeros. The output Y must be available at every rising edge of CLK and the latencies for all functions is 1 cycle. Inputs of ALU: CLK, RST, 8-bit unsigned A, 8-bit unsigned B, 4-bit unsigned SEL Output of ALU: 8-bit unsigned Y Function table of ALU is given below: Function SEL Operation Number ] 2 3 4 5 6 7 8 9 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 YA Y<=A+B Y<=A+Bbar YA and B Y<A or B Y<=Axor B Y< Abar Ys=shl A Y<=shr A Y<=0 Go to OpenLane folder Sed -/Openlane Ssudo make mount. Now Openlane docker is started S/flow.tel -design alu-init_design_contig package require openlane 0.9 %prep - design alu %run synthesis Sru_lourplan %run placement Srun_cts The whole functions can be implemented using a single case statement even if it is not an optimal way of doing it. You are free to implement them in your way. You can ignore the carry out in addition operations. run routing Srun magic run_magic_spice_export run magic dre %run lvs run antenna_check. A. (35 Points) Implement the given ALU entity in VHDL language. Provide your VHDL code. (35 Points) Implement the given ALU module in Verilog language. Provide your ende. C. (30 Points) Implement the given ALU using OpenLane Design Flow. Hint: Install OpenLane and Magic tools into your Linux machine as described in the class. Create required design files (alu.v, config.tel and sky130A_sky130_fd_sc_hd_config.tcl) and run the following commands those are also described in the class. Function This command creates an alu folder under /designs folder Copy and modify the design files to this folder same as other example designs flow.tel-interactive Transfer A Addition A plus l's complement of B Logical AND Logical OR Logical XOR Complement A Shift left A Shift right A Transfer 0's Go to this folder Sad -/Openlame/designs/counter/runs/..../results/finishing Run magic Smagic -T sky 130A lef read../../tmp/merged lef def read alu.gds & After completion of flow without any error you can run mugic to see GDSII of your design. Open a new terminal and run the following commands. Make sure nor error is generated throughout the flow. set env(IP SIZING) "absolute" set enviDIE AREA) "0 0 100.0 100.0" In the first part of design, let's make the DIE_AREA is absolute and 100 mx100um and set clock frequency to 200MHz.. You can do it hy setting the following parameters. set enviCLOCK PERIOD) "x" */Openlane/designs/alu/runs/name_of_run/reports/synthesis */Openlane/designs/alu/runs/name_of_run/logs/synthesis Provide the screenshot of GDSII file for designed ALU. Provide synthesis statistics, and STA (setup time and hold time analysis) results. They can be found at the following directories: In the second part, lets change DIE_AREA to 75umx100um and rerun the flow. Provide the GDSII for this run as well.