1) As a computer architecture/ organization expert, you are expected to execute the algorithm for reversing the words in a sentence and storage of the reversed sentence in an array using microprocessor without interlocked pipelined stages RISC assembly code. As much as you can, present the high-level and the microprocessor without interlocked pipelined stages assembly codes succinctly.

2)In identifying the different types of cache, using a practical scenario, specify the merit(s) they may have over each other. In your view, do you consider it possible to cache addresses used for memory-mapped input/output? It may also interest you to identify the merit(s) and demerit(s) of virtual memory systems.