1. Consider the following MIPS assembly code below. as_loop: bge $t0, $al, as_done sll $t1, $t0, 2 #i* 4 add $t1, $a0, $t1 # &array[i] lw $t1, 0($tl) # array[i] add $v0, $v0, $t1 # sum += array[i] add $t0,$t0, 1 # ++i j as_loop as_done: jr $ra a) Identify all of the RAW, WAR, and WAW hazards. b) Remove the false dependencies through register renaming. Rewrite the code with your renamed registers. c) Assuming a scalar pipeline that executes the code above for one full iteration (an iteration in the middle- not the first or the last), calculate the number of cycles needed before and after renaming. You may assume a simple 5 stage pipeline, where each stage takes one cycle. 1. Consider the following MIPS assembly code below. as_loop: bge $t0, $al, as_done sll $t1, $t0, 2 #i* 4 add $t1, $a0, $t1 # &array[i] lw $t1, 0($tl) # array[i] add $v0, $v0, $t1 # sum += array[i] add $t0,$t0, 1 # ++i j as_loop as_done: jr $ra a) Identify all of the RAW, WAR, and WAW hazards. b) Remove the false dependencies through register renaming. Rewrite the code with your renamed registers. c) Assuming a scalar pipeline that executes the code above for one full iteration (an iteration in the middle- not the first or the last), calculate the number of cycles needed before and after renaming. You may assume a simple 5 stage pipeline, where each stage takes one cycle