$1)$ Create a verilog module to simulate the following expression F$=($A$+$B$)($A$\text{'}+$C$)+$AD$+$E$,$ assume all gates have a propagation delay of $10$ns$,$ and F$1$ where F$1$ has fixed all hazards from F$.$

$2)$ Create a test bench that shows all hazards in F and that they are fixed in F$1$

$3)$ Create a test bench file that outputs a truth table to verify that F $=$ F$1$ for all inputs of ABCDE. This may be included in the same test bench as $2$ or in a separate file.

Bonus: Instead of using a fixed delay for each gate set the delay for each gate such that the circuit has all three types of hazards $($static $0,$ static $1,$ and dynamic$).$ Hint use separate rising and falling propagation delay, #$($t$\_$rise, t$\_$fall$)$ Upload Assignment: Verilog Project $\backslash$#$1$

INSTRUCTIONS

$1.$ Create a verilog module to simulate the following expression $\backslash (\backslash$mathrm$\{$F$\}=(\backslash$mathrm$\{$A$\}+\backslash$mathrm$\{$B$\})\backslash$left$(\backslash$mathrm$\{$A$\}^\{\backslash$prime$\}+\backslash$mathrm$\{$C$\}\backslash$right$)+\backslash$mathrm$\{$AD$\}+\backslash$mathrm$\{$E$\}\backslash ),$ assume all gates have a propagation delay of $10$ ns $,$ and F$1$ where F$1$ has fixed all hazards from F$.$

$2.$ Create a test bench that shows all hazards in $\backslash ($ F $\backslash )$ and that they are fixed in $\backslash ($ F $1\backslash )$

$3.$ Create a test bench file that outputs a truth table to verify that $\backslash ($ F$=$F $1\backslash )$ for all inputs of $\backslash ($ A B C D E $\backslash ).$ This may be included in the same test bench as $2$ or in a separate file.

Bonus: Instead of using a fixed delay for each gate set the delay for each gate such that the circuit has all three types of hazards $($static $0,$ static $1,$ and dynamic$).$ Hint use separate rising and falling propagation delay, $\backslash$#$($t$\_$rise, t$\_$fall$)$

truth table.PNG

Hazards.PNG