$1.$ Design a $1024-$word X $32-$bit "dual$-$port" SRAM using Verilog. Dual$-$port SRAM has two sets of

interfaces, enabling simultaneous memory access. Each interface set supports both read and write

operations. However, if both interfaces attempt to write to the same address simultaneously, the request

from the second interface $($En$1)$ will be ignored. This design is an extension of the SRAM discussed in

Lecture Slide $7-1,$ page $14.$

a$)[70$ pts$.]$ Provide your Verilog code.

b$)[30$ pts$.]$ Include detailed comments to your code to describe the logic you implement.