$1.$ Design a $32-$bit datapath for a special$-$purpose processor $($SPP$)$ that performs the algorithm listed in the pseudo$-$code above.

a$.$ Since there are eight $7-$segment displays, the maximum answer from the factorial calculation that we can display on the board will be FFFFFFFF $($which is $4,294,967,295$ decimal$).$ So$,$ the maximum input that we can accept for which we can calculate the factorial and display the answer on the board would be $12$ since $12!$ is $1$C$8$CFC$00(479,001,600$ decimal$)$ and $13!$ is $17328$CC$00(6,227,020,800$ decimal$)$ which would require $9$ digits to display.

b$.$ This means that the entity should accept a $4-$bit input even though the internal data path should be a $32-$bit bus which means you will need to concatenate $28$ bits of zeros to the beginning of the input into the rest of the circuit. Include in your design an overflow bit output which will be high if the input is invalid, that is$,$ it will produce an output greater than FFFFFFFF; this overflow bit should go high whenever the input is too large. You may use the built$-$in multiplication operator $*$ in the IEEE.std$\_$logic$\_$unsigned.all library instead of designing your own multiplier $($refer to example $34$b in the book$).$ Implement the datapath using VHDL$.$