$1/$ DO NOT EDIT THE CODE ABOVE

FOR THIS LAB USE: SW$[$W$-1$:$0],$ SW$[9],$ KEY$[1]$ and KEY$[0]$ as inputs; HEX$5[7],$HEx$3[0]$ and For your structural design:

declare the necessary wires first coutputs of G$1$ and G$2$; output ports can b

provide one line of verilog for every gate $(5$ gates then $57$ines$)$

PUT ALL YOUR CODE BELOW THIS LINE

wire wire$\_1,$ wire$\_2$;

assign $wir{e}_1=($&$5w[2$:$0])$;

assign $wir{e}_2=|$ KEY$[1$:$0]$; $(Y)or$ simp$|$

PUT ALL YOUR CODE ABOVE THIS LINE