1. Draw the complete circuit for a 4-bit wide 4 to 1 multiplexer circuit using only AND, OR, and Not gates. 4-bit wide means that each data input signal is four bits and the output Y is four bits. 2. Write the complete data flow Verilog code for an 8-bit wide 4-to-1 multiplexer circuit. 3. Use a truth table to show that the following equation is true: Xiyi + ci(xi + Yi) = XiYi + C(xi yi) 4. Draw the complete 4-bit ALU circuit having the following operations. Use K- maps to reduce all of the equations to standard form. $2$150 Operations 0 0 0 0 0 1 1 1 1 0 1 0 A plus B 1 A' Pass A Pass B through the AE 0 1 1 0 0 1 A-1 1 1 A - B 0 1 A XOR B A NAND B 5. Draw the circuit for the 2-to-4 decoder with enable.